The present invention concerns a procedure for conveying to a processor system the input and output data of a process or of other computer-controlled pieces of apparatus or installations, said system comprising one or several central units with memories.
In numerous control systems employing computers, as may be found in industrial processes as well as in complex equipment, such as cranes or other installations, it is advisable to distribute various tasks among different central units. It is similarly advantageous to subdivide various controls of portions of apparatus of or entire apparatus. Such subdivison simplifies programability and provides a simpler system which is easy to service and to modify. In the interest of clarity, it is desirable to specify precisely the terms "computer", "central unit" and "processor" from the viewpoint of the present invention. A computer is understood to be an entity composed of one or several central units with ancillary equipment and the central unit, again, consists of one or several processors with ancillary equipment. In the control systems mentioned, frequently two or more central units need the same input and output data from a processor, or data describing the state of the apparatus at a given time. For instance, the state of a single limit switch may be needed by one or several central units so that control can be properly managed.
In the prior art, this problem in control systems has been solved, either by connecting all requisite input and output data directly to all central units needing them or by connecting the central units together by means of some kind of data transfer bus, or even by using a separate input/output processor (to be referred to in abreviation, as I/O processor in the following), by which all central units receive all the data which they need. All these arrangements have their own drawbacks, however: when the input and output data are directly connected to all central units, it becomes necessary to construct for all of them similar input and output circuits. This increases the manufacturing costs and renders the circuitry complex. If each input and output datum is connected to only one central unit and a data transfer bus is used, these costs may be reduced, but now arises the problem of the interfacing between central units, the costs thereby incurred, and often also the slow operation caused by the bus. On the other hand when an I/O processor is used, there appear as extra costs those of the I/O processor itself, and the problem is then the interfacing of the central units and the I/O processor to attain the higher speed of operation which the I/O processor permits when there are several central units. For taking care of such interfacing, DMA (Direct Memory Access) technique or the traditional I/O technique has been used.